Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning

Abstract As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are the most effective and popular techniques to reduce interconnect delay and are traditionally applied to post-layout optimization. As the SIA technology roadmap predicts, however, the number of interconnections among different blocks and that of buffers inserted in a chip for performance optimization will grow dramatically [17, 18]. It is obviously infeasible to insert/size hundreds of thousands buffers or wires during the post-layout stage when most routing regions are occupied. Therefore, it is critical to incorporate buffer-block and wire-size planning into floorplanning to ensure timing closure and design convergence. In this paper, we first derive continuous buffer insertion/sizing and wire sizing formulae for performance optimization under a more accurate wire model, and then apply the formulae to interconnect-driven floorplanning that considers not only the buffer-block planning addressed in [7], but also wire-size planning. Experimental results show that our approach achieves an average success rate of 93% of nets meeting timing constraints and consumes an average extra area of only 0.8% over the given floorplan, compared with the average success rate of 73% and extra area of 1.20% resulted from recent work in [7].